This invention relates to MOS-type transistors, and more specifically relates to a novel MOS transistor, hereafter called a VD-MOS transistor which offers advantages over other MOS transistors.
The device of the present invention is particularly useful in the fabrication of large scale integrated (LSI) circuits for various applications. Such LSI circuits commonly employ various types of MOS transistors. Among the recent types of MOS transistors introduced for possible LSI use are the V-MOS and D-MOS transistors which with their applications are described in an article appearing at pages 74 to 81 of ELECTRONICS, April 1, 1976. The V-MOS transistor is also described in U.S. Pat. No. 3,924,265 to T. J. Rodgers.
In the D-MOS device, a double-diffused doping profile is formed in the wafer below the gate region to form a short channel extending along the length of the wafer. Note that a double ion implantation could also be used and it is intended that the term double-diffusion, used hereinafter, includes the double ion implantation process. The D-MOS device is capable of very high device density, much higher than that of the bipolar transistor but the device is not as fast as the bipolar transistor (e.g. 0.5 nsec per gate delay). However, the fabrication of the D-MOS device is complex and hard to control so there is often poor manufacturing yield. A major reason for the poor yield is that the cross-over point in the double diffusion profile of the D-MOS is not accurately controllable so that the threshold voltage can vary greatly.
The V-MOS device is well known, wherein a V-shaped notch is placed in the wafer surface to allow access to a substrate-level MOS source element while the drain and gate structures are formed on the slopes of the notch. This vertical arrangement of the active elements of the device permits a compact arrangement of devices in a wafer, and the technique allows an increase in device density over that of bipolar circuit elements. The major limitation of V-MOS devices is that only the common source configuration is allowed because of the common back of the wafer electrical contact.
In summary, the D-MOS devices have yield and voltage threshold problems while the V-MOS have very limited circuit design applications because of the common back contact.